Memory devices have typically been developed with emphasis on high integration and large capacity frameworks, while central processing units (CPUs) have typically been developed with emphasis on high speed operation, which has led to large disparities between the operating speeds of memory and CPU systems. In this regard, despite the implementation of high-speed CPUs, the overall performance of computer systems have been limited, primarily in part, by the lower operating speeds of memory devices. Accordingly, memory systems are now being developed with more emphasis on high speed and high-performance operation, to provide increased data input/output per unit time. In general, high performance memory systems are realized by implementation of high speed memory devices together with data I/O interfaces that enable high speed data transfer between the memory devices and other system components.
FIG. 1 schematically illustrates a conventional framework of a semiconductor memory system. In particular, FIG. 1 depicts a conventional framework of a DRAM (Dynamic Random Access Memory) with a shared data I/O network. Referring to FIG. 1, the memory system generally comprises a plurality of memory banks 10A, 10B, 10C, 10D, where each memory bank has an independent data input/output network connected to a global data input/output network shared among the memory banks, as explained hereafter,
Each bank 10A˜10D includes a memory array comprising a plurality of wordlines, WL0, WL1 . . . (or generally, WL) extending in a row direction and a plurality of bit line pairs BL/BLB extending in a column direction, and a plurality of memory cells MC arranged in a matrix in a region where the wordlines WL intersect the bit line pairs BL/BLB. Each bit line pair BL/BLB is connected to a bit line sense amplifier 13.
When a word line WL is enabled by an active command of a row address strobe signal /RAS, the data stored in each memory cell MC in the row of memory cells connected to the word line WL is transmitted to corresponding bit lines BL and BLB. Data of memory cells connected to an enabled word line WL are charge-shared to bit lines BL, slightly increasing or decreasing a voltage level of bit lines BL and BLB. The bit lines BLB of memory cells individually adjacent to the bit lines BL are “complementary bit lines”, which maintain a voltage level precharged to a reset bit line voltage. The variation in the voltages loading on a given bit line pair BL/BLB is sensed and amplified by the sense amplifier 13 connected to the given bit line pair BL/BLB to thereby read the data of a memory cell connected to the activated WL.
The output of the bit line sense amplifier 13, bit lines BL and BLB, are selected by a column selection circuit that is activated by an active command of a column address strobe signal /CAS. The data of bit line BL and complementary bit line BLB sensed by the bit line sense amplifier 13 is coupled to a local data input/output line pair LIO/LIOB in response to a column selection signal CSL. The local data input/output line pair LIO/LIOB of a given memory bank 10A˜10D is selectively connected to a global data input/output line pair GIO/GIOB by operation of corresponding selection blocks 15A˜15D (or generally, 15i), which part of a switching circuit. The switching circuit may be configured as a multiplexer (MUX). In essence, the local data input/output line pairs LIO/LIOB of the memory banks 10A-10D are individually connected to, and share, the global data input/output line pair GIO/GIOB, and the global data input/output line pair GIO/GIOB is shared by the plurality of memory banks 10A˜10D.
The global data input/output line pair GIO/GIOB is connected to a data sense amplifier 17. The switching circuit determines which memory bank 10A˜10D will be connected to the data sense amplifier block 17. The data transferred to the data sense amplifier 17 through the global data input/output line pair GIO/GIOB is sensed and amplified by the data sense amplifier 17, and then output through an output buffer.
FIG. 2 schematically illustrates is a circuit diagram of a selection block 15i of FIG. 1. The selection block 15i includes a load block 19, a switching block 20 and a bank switch control block 16. The load block 19 includes two load transistors P10 and P11 having drain/source terminals connected between a power source voltage terminal VDD and respective local input/output data lines LIO/LIOB, and gate terminals that are grounded.
The switching block 20 includes P-type transistors P12 and P13 that operate as switches under control of the bank switch control block 16. The transistor P12 selectively connects the local data line LI0 to the global data line GIO, and the transistor P13 selectively connects the local data line LI0B to the global data line GI0B. The switching operation is controlled by a bank selection control signal PWRD_i applied from the bank switch control block 16. The bank switch control block 16 is a delay circuit that receives as input bank selection signal CAB_i which is generated in response to a memory bank address signal, and then outputs the bank selection control signal PWRD_i.
Current applied through the load block 19 by using the switching block 20 flows to each of the global data input/output line pair GIO/GIOB through the local data input/output line pair LIO/LIOB. The current volume flowing through the global data input/output line GIO and the complementary global data input/output line GIOB is different based on the data value transmitted to the local data input/output line pair LIO/LIOB.
FIG. 3 is a circuit diagram illustrating a data sense amplifier 17 of FIG. 1. In general, the data sense amplifier 17 includes a current sense amplifier 23 and a voltage sense amplifier 25. The current sense amplifier 23 is a type of data line sense amplifier that is used when data is transmitted through current. When the current sense amplifier 23 shares multiple memory banks, the length of the data line is increased and thus, transmission of data using a current signal improves the transmission speed of data through the data line. The current sense amplifier 23 senses and amplifies the current of the global data input/output line pair GIO/GIOB, and determines a voltage level of internal data input/output line pair IDIO, IDIOB.
The current sense amplifier 23 is operable in a semiconductor memory device having low power source voltage. The current sense amplifier 23 includes sensing transistors P14 and P16, a voltage device 21 including N-channel transistors N12 and N14 (which change an input current to a voltage), and a switching transistor N10. The sensing transistors P14 and P16 are formed to have matching electrical characteristics. The source terminals of transistors P14 and P16 are respectively connected to the global data input/output lines GIO and GIOB. The gate and drain terminals of transistors P14 and P16 are cross connected. The drain terminals of transistors P14 and P16 are connected to internal data input/output line pair IDIO/IDIOB to transfer an output of the current sense amplifier 23 as an input voltage to a latch-type sense amplifier 25 provided as a type of voltage sense amplifier.
The N-channel transistors N12 and N14 of the voltage device 21 are formed to have matching electrical characteristics. The transistors N12 and N14 are individually connected between the internal data input/output line pair IDIO/IDIOB and the switching transistor N10, and have gate terminals that are connected to a power source voltage. In the voltage device 21, the internal data input/output line IDIO and the complementary internal data input/output line IDIOB have mutually different voltage levels, and these voltage levels are transferred to the voltage sense amplifier 25 and are then latched therein. The voltage sense amplifier 25 has a standard configuration well-known by those skilled in the art. The voltage sense amplifier 25 is enabled by a data sense amplifier enable signal DSAEN, and latches a voltage level transferred from the current sense amplifier 23.
The switching transistor N10 is selectively activated in response to a sensing enable signal PIOSE. When activated, the switching transistor N10 provides a current path through which current of a given volume supplied by the load block (19 of FIG. 2) flows to ground.
FIG. 4 is a timing diagram that illustrates a bank interleave operation of the memory system of FIG. 1. Referring to FIG. 4, in the multi-bank semiconductor memory device of FIG. 1, it is assumed that an external clock signal ECLK is inputted, and a read signal ARD of the first bank 10A, a read signal BRD of the second bank 10B, a read signal CRD of the third bank 10C, and a read signal DRD of the fourth bank 10D are sequentially applied as a command signal COMMAND. Column selection signals CSL_a, CSL_b, CSL_c and CSL_d of respective banks are sequentially applied following the respective memory bank read signals ARD, BRD, CRD and DRD.
Further, respective bank selection control signals PWRD_i for the memory banks 10A˜10D are enabled before respective column selection signals CSL are enabled, to thereby connect respective memory banks 10A, 10B, 10C, 10D to the global data line pair GIO,GIOB. In particular, as depicted in FIG. 4, the bank selection control signals PWRD_a˜PWRD_d are sequentially enabled (logic low) and disabled (logic high) such that the enabled periods of such signals are non-overlapping. The column select signals CSL_a˜CLS_d are enabled (logic high) and disabled within the enabled periods of respective bank selection control signals PWRD_a˜PWRD_d.
The local data input/output line pair LIO, LIOB and the global data input/output line pair GIO, GIOB are connected when the bank selection control signals PWRD_a, PWRD_b, PWRD_c, PWRD_d are enabled, and the current sense amplifier 23 (FIG. 3) operates to apply a voltage level corresponding to data to an internal data input/output line pair IDIO, IDIOB. With a voltage level corresponding to data of the internal data input/output line pair IDIO, IDIOB, data is sensed by enabling the data sense amplifier by an enable signal DSAEN in the voltage sense amplifier 25 (FIG. 3).
In the conventional multi-bank semiconductor memory device described above, current signals sequentially input by read data values are inputted to the data sense amplifier 17 after a bank selection control signal PWRD_i is enabled, and then a determined time lapses. In this case, when sensing the data of the selected memory banks, the margin for sensing data of the last memory bank is smaller by an amount indicated by the circled region 27 in FIG. 4. In particular, a given period of time is required to form a current path by a signal of memory bank when a bank selection control signal PWRD_i is enabled and to reach the current sense amplifier 23 of the data sense amplifier 17. Consequently, when there is no enabled bank selection control signal PWRD_i, a global data input/output line pair GIO/GIOB is not connected to any memory bank. In such instance, no current path is formed and the voltage device 21 (FIG. 3) rapidly discharges an internal voltage. As depicted in FIG. 4, the global data lines GIO/GIOB are continuously loaded with current due to the sequential, and continuous application of the first three bank selection control signals PWRD_a, PWRD_b and PWRD_c. But when the last signal PWRD_d is disabled, there is no continuous current path for the data signal of the last selected bank (e.g., bank 10D) and thus, the input data valid window for sensing the data of the last memory bank is relatively smaller than the input data valid window for sensing data signals of the previously, continuously selected banks, thereby resulting in an operating frequency limit in a data sensing.